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Short Programs

High-Speed I/O Design Techniques [6.22s]

Date: TBD, 2012* | = Tuition:=20 $2,000 (tentative) | Continuing Education Units (CEUs): 1.8 = (tentative)

*This class is tentatively planned = for 2012=20 depending on the level of interest. Email the Short=20 Programs office to express your interest in taking this course. = Please=20 include your industry and learning goals.

Course Summary

This course covers the circuit and system design of equalized = high-speed=20 I/Os. Today's high-speed interfaces are limited by the bandwidth of the=20 communication channel, tight power constraints, and noise sources that = differ=20 from those in standard communication systems. The wire bandwidth = limitations=20 make straight circuit solutions inefficient and the power and area = constraints=20 make standard digital communication approaches infeasible. Efficient = solutions=20 require bridging the fields of digital communications, optimization,=20 statistical, and dynamic system modeling with system architecture, = mixed-signal,=20 and digital circuit design. This course will lay the groundwork for this = type of=20 system-driven I/O design by covering each of the required layers in link = system=20 hierarchy. =20

Basics of channel properties are introduced first followed by = modeling,=20 measurements, and communications techniques. The course then focuses on = different link equalization techniques, comparing them both from system=20 perspective and from the performance of resulting circuit = implementations. Some=20 examples will cover trade-offs between transmit pre-emphasis and=20 decision-feedback equalization, linear analog receiver equalization, as = well as=20 joint modulation/equalization and equalization/coding techniques (like = PAM4,=20 duobinary and multitone signaling). Implementations of transmitter FIR=20 equalizers, several DFE receiver topologies, and peaking amplifiers will = be=20 discussed in detail. Several adaptive techniques for equalizer tuning = and link=20 monitoring will also be presented.

Content

3D"Fundamentals" Fundamentals: = Core=20 concepts, understandings and tools (35%)

3D"Latest Latest = Developments:=20 Recent advances and future trends (25%)

3D"Industry Industry = Applications:=20 Linking theory and real-world (40%)

Delivery Methods

3D"Fundamentals" Lecture: = Delivery of=20 material in a lecture format (50%)

3D"Latest Discussion or = Groupwork:=20 Participatory learning (10%)

3D"Industry Labs: = Demonstrations,=20 experiments, simulations (40%)

Level

3D"Fundamentals" Introductory: = Appropriate=20 for a general audience (15%)

3D"Latest Specialized: = Assumes=20 experience in practice area or field (55%)

3D"Industry Advanced: = In-depth=20 explorations at the graduate level = (30%)

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Learning Objectives

The participants of this course will be able to: =09

Understand the components of a typical high-speed link channel and = relate=20 them to link performance and overall channel response.
Construct an open-loop and adaptive equalizer to correct for the = channel=20 frequency selectivity.
Apply different inter-symbol and noise models and run statistical=20 simulation of link performance.
Understand basic concepts in link transmitter and receiver circuit = design.
Describe trade-offs and design of advanced transmit and receiver=20 equalization circuits.
Extract key trade-offs between inter-symbol interference and = circuit=20 induced noise for different modulation and equalization = techniques.
Analyze state-of-the-art methods for link data and clock = recovery.
Apply adaptive equalization algorithms.
Construct a real-time behavioral simulation of critical link = blocks=20 (adaptive equalizer, clock and data recovery).
Analyze circuit behavior of critical link circuits through circuit = simulation.

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Who Should Attend

This course is targeted towards integrated circuit, system, and=20 signal-integrity engineers and students who wish to gain better = understanding of=20 all the layers involved in design of high-speed interconnects. It can = serve=20 both as an entry point into the area and also as a review of the=20 state-of-the-art practices in high-speed I/O design, both in industry = and=20 academia. A basic background in electrical engineering is required.

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Program Outline

This course consists of 2 days of instruction and 1 day of labs in = link=20 performance simulation, system and circuit design of most critical = blocks.

Day 1
Background and Motivation; Link = Channel=20 Environment; Equalization and Modulation

1. Introduction

2. Background and Motivation

a. I/O link applications

b. Channel properties

c. Transmitter and receiver overview

d. Circuit limitations

3. Link Channel Environment

a. Description of link channel environment (transmission lines, = connectors,=20 packages)

b.Basic transmission line theory

c. Lossy transmission lines (skin-effect, dielectric loss,=20 edge-roughness)

d. Understanding impedance discontinuities and reflections

e. Impact of packages and on-chip terminations

f. Channel component design examples

g. Putting it all together

4. Equalization and Modulation

a. Understanding the inter-symbol interference and cross-talk

b. Linear equalization algorithms

c. Decision feedback equalization algorithms

d. Adaptive equalization

e. Multi-level modulation on bandlimited channels

f. Partial-response signaling =

Day 2
Link Modeling; Lab 1 =20

1. Link Modeling =20

a. Overview of current models (worst-case, standard statistical) =

b. Accurate statistical modeling of intersymbol-interference and = cross-talk

c. Timing noise modeling

d. Bit-error rate modeling =

2. Lab 1 =20

a. Design of linear and decision-feedback equalizers (Matlab = simulations)=20

b. Multi-level signaling =

c. Statistical link modeling simulations (Matlab) = =20

d. Adaptive equalization (Matlab/CppSim) = =20

Course Participant Dinner at a Local Restaurant

Day 3
Link System = Implementations=20 (Equalization, Clock Recovery); Lab 2

1. Link System Implementations

a. Link system design (equalizer type trade-offs, adaptive = equalization,=20 back-channel)

b. Transmitter implementations (driver design, transmit = pre-emphasis)

c. Receiver implementations (pre-amplifier, decision circuits,=20 decision-feedback)

d. Clock and data recovery

e. Link monitoring and adaptation circuits

2. Lab 2

a. Link behavioral simulations (decision-feedback equalizer and=20 data-recovery)

b. Circuit simulations =96 filtering and sampling receiver = implementations=20 (pre-amplifier, decision circuits, loop-unrolled decision-feedback) = =20

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Course schedule, registration times, special = events

Class runs 9:00 am - 5:00 pm each day.

Registration is on Monday morning from 8:00 - 8:45 am.

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About The Lecturers

Vladimir Stojanovic
Professor Vladimir Stojanovic = is an=20 Assistant Professor of Electrical Engineering and Computer Science at = MIT and a=20 principal investigator in the Research Laboratory of Electronics (RLE) = and=20 Microsystems Technology Laboratories (MTL). He received the Dipl. Ing. = from the=20 University of Belgrade in 1998, the M.S.E.E. and Ph.D. from Stanford = University=20 in 2000 and 2005 respectively. From 1999 to 2004, he was Principal = Engineer in=20 the Logic Interface Division of Rambus, Inc.

His current research = interests include design, modeling, and optimization of integrated = systems, from=20 standard VLSI blocks to CMOS-based electrical and optical interfaces. He = is also=20 interested in design and implementation of digital communication = techniques in=20 high-speed interfaces and high-speed mixed-signal IC design. He leads = the=20 Integrated Systems Group at MIT.

At Stanford, Prof. Stojanovic = was=20 engaged in circuit and system design of high-speed electrical links,=20 hierarchical modeling and convex optimization of VLSI systems, and = system design=20 of modal compensation techniques in multi-mode fiber links. At Rambus, = Vladimir=20 was one of the main contributors to the development of Rambus=92 next = generation=20 high-speed serial link technology (circuit and systems techniques for = adaptive,=20 equalized links, with multi-level modulation and advanced clock and = data=20 recovery). He holds 10 patents in the area of high-speed circuits and = serial=20 links.

For more information on Prof. Stojanovic=92s research and = teaching=20 activities you may visit http://www.rle.mit.edu/isg.

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Location

This course takes place on the MIT campus in Cambridge, = Massachusetts. We can=20 also offer this course for groups of employees at your location. Please = contact =20 the Short Programs office for further details.

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Updates

There are no updates at this time.

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