Low-Power Engineering Community = =C2=BB Blog Archive=20 =C2=BB The Deafening Problem Of High-Speed I/O

The Deafening Problem Of High-Speed I/O

By Ann Steffora Mutschler
The performance of digital systems today = is=20 limited by the interconnection bandwidth between chips, boards, and = cabinets.=20 This has driven I/O speeds up into the gigabytes. While this boosts = performance,=20 it also opens the door to a host of new problems within the chip, board = and=20 system. Add low-power requirements to the mix and it is a recipe for = huge=20 headaches.

One of the most rapidly emerging problems with high-speed I/O is the=20 integrity of the power being delivered to the ICs. =E2=80=9CIn attempts = to lower power=20 while increasing the speed, power voltages are going lower even to = sub-1V=20 voltage levels. As the voltages become lower, the tolerances become more = difficult to meet. Therefore the ability to deliver sufficient and clean = power=20 to the ICs is an ever-increasing problem,=E2=80=9D explained Patrick = Carrier, technical=20 marketing engineer in the systems design division of Mentor = Graphics.

Noise matters, too. Lowering power is like filling a room with = equipment that=20 is more sensitive to noise. =E2=80=9CWhen you go into process nodes of = 28nm, for=20 example, you are now down to core voltage supplies of about 1v or 0.9v, = and when=20 you are operating at these really low voltages you universally have a = problem of=20 noise because you are dealing with threshold voltages that have a much = lower=20 difference. The noise coming in, whether it was from the same or from = the=20 high-speed I/Os, the noise is the same or larger proportional to the = voltage,=E2=80=9D=20 noted Eric Huang, product marketing manager for USB digital cores at=20 Synopsys.

EDA Consultant Les Spruiell agrees. =E2=80=9CThe biggest problem with = high-speed I/O=20 is driving something that is off-chip, which means there is a lot of = impedance.=20 It requires a lot of power to get nice sharp clean edges. People build = up their=20 chip in different voltage domains so the I/O will have a higher voltage=20 typically than the core logic. As the power to the core logic is lowered = the=20 overall power usage of the system drops. However, this still creates an = enormous=20 amount of noise, especially with gigabyte transfer rates, because as the = switching is happening that fast the noise is banging on the overall = power. If=20 you are not careful it will get back up through and into your core = logic. As the=20 voltage in the core logic drops, the same amount of noise is = worse.=E2=80=9D

Compounding this problem is the fact that many different levels of = voltage=20 (and grounds) must be delivered to the ICs forming very complex power=20 distribution networks (PDNs) on the PCB. =E2=80=9CWe have some customers = that are=20 required to put more than 30 unique PDNs on a single PCB. This requires=20 sophisticated power integrity analysis on the PCB that can simulate both = DC and=20 AC conditions, and allow the designer to adjust the design to assure = clean and=20 sufficient power delivery,=E2=80=9D Mentor=E2=80=99s Carrier said.

Other high-speed I/O problems include system timing, which is = especially true=20 for DDR2 and DDR3 interfaces that have very complicated timing = relationships,=20 and timing margins measured in picoseconds, as well as qualifying SerDes = and=20 trying to meet bit error rate requirements in the sub 1=C3=9710^-15 = range, optimize=20 pre-emphasis and equalization settings, and test performance on links = that can=E2=80=99t=20 be measured at the die.

=E2=80=9CWe can segment this problem into two parts,=E2=80=9D said = Aveek Sarkar, vice=20 president of product engineering and support at Apache Design Solutions. = =E2=80=9CThe=20 first is where you need a lot of buffers for switching at the same time. = If you=20 have a 64-bit interface and you switch 56 at the same time, there is a = lot of=20 effect on the propagation of the signal. In the past we were mostly = worried=20 about crosstalk. Now, we=E2=80=99ve got a power integrity issue. The = number of buffers=20 is increasing in the I/O ring and the package/board designs are using = fewer=20 layers because of cost. On top of that, the DCap efficiency is going = down. So=20 with a high-speed I/O interface you=E2=80=99ve got to model the I/O, the = buffer, the=20 package and board parasitics and the receiver and then simulate the = jitter from=20 switching in the I/O ring.=E2=80=9D

To deal with these issues, two forms of power integrity analysis are = needed.=20 DC drop analysis can be used to analyze the PDN from the voltage supply = to all=20 the IC pins requiring that voltage level to identify places in the PDN = where the=20 voltage level will be below acceptable levels. They can be increased by=20 modifications to the PDN shape, with possible modifications such as the = addition=20 of more metal or additional power vias.

=E2=80=9CIncluded in this analysis are results showing current = density, which=20 highlights neck-downs in the PDN that may result in higher than = acceptable=20 current density. This will affect the DC drop and may also result in a = situation=20 where the neck-down can overheat over time and cause either PCB = de-lamination or=20 fusing. Again either more metal or power vias can solve the = problem,=E2=80=9D he=20 explained.

Another type of analysis is AC analysis where switching of the IC can = result=20 in current spikes and produce waves along the PDN, Carrier noted. = =E2=80=9CThis can=20 result in PDN voltages that are not clean (beyond tolerance) or even = affect=20 signal carrying interconnects adjacent to the PDN. The addition of = decoupling=20 caps or stitching vias, modification of cap mounting and/or location, = changes in=20 stackup including use of different dielectric materials, can correct = this=20 problem.=E2=80=9D

As system timing requires understanding of flight times on the = PCB=E2=80=93delays of=20 each signal as it passes through the board and is affected by board = stackup,=20 loading, and crosstalk. This can be taken a step further and = automatically=20 integrated with on-chip timing and margin analyzed. Further, SerDes=20 qualification can be done through simulation of SerDes buses.

Synopsys=E2=80=99 approach is to figure out whether power domains = have been properly=20 isolated by taking in the user power intent specification via UPF. The=20 specification can include power domain information along with power = management=20 cells (also known as special cells such as ISO, LS, retention register)=20 strategies. The goal is to check power domains and special cells to = ensure that=20 the power management cell strategies are properly inserted, said Mary = Ann White,=20 director of Galaxy Power marketing at Synopsys.

High-speed I/O issues require dedicated = resources
Dealing=20 with high-speed I/Os is complicated, though, and due to the speeds being = used=20 the design must be finely tuned. That puts tremendous pressure on the=20 designers.

Within design teams today there is a group of people that do nothing = but=20 focus on the I/O pad, Spruiell said. =E2=80=9CWhen you get into = flip-chip packaging it=20 used to be that the I/O pads were all around the edge of the chip, but = that is=20 not true anymore. You could theoretically have an I/O pad banging away = in the=20 core of your chip, and getting that isolation down is a tough problem. = Typically=20 it is a small group of analog experts that treat the I/O path pretty = much as an=20 analog/mixed signal problem because you have to balance so many = different=20 things. It isn=E2=80=99t just =E2=80=98turning on a logic gate,=E2=80=99 = =E2=80=98turning off a logic gate.=E2=80=99=20 When that thing switches and the power starts flowing out of the chip, = it has a=20 tendency to yank down the power grid, which affects stuff around it. = It=E2=80=99s like=20 being on a trampoline. If I am bouncing on a trampoline and there is = nobody else=20 there, I don=E2=80=99t have a problem. But if you put somebody else on = the trampoline=20 then you end up with a problem.=E2=80=9D

Related to this, the pads must be isolated from each other because = they are=20 connected to a common voltage domain. =E2=80=9CYanking on one will cause = a yank on the=20 other so it becomes a very delicate balancing problem,=E2=80=9D he = explained. =E2=80=9CThis is=20 why companies like Xilinx with their big Virtex chip spend a huge amount = of time=20 on getting those signals on and off chip because the core of what they = do is=20 programmable=E2=80=94the core logic elements themselves are fairly = adaptable to custom=20 digital design techniques.=E2=80=9D

To do the isolation, Synopsys=E2=80=99 Huang explained that there = must be enough pads=20 and pins. =E2=80=9CFor example, you might have a number of pads for the = analog logic=20 with their own voltage supply. You need to have separate power domains = for each=20 element in your chip, whether it=E2=80=99s a PHY or the digital logic. = By having=20 separate power domains you isolate and decouple the different things so = that you=20 don=E2=80=99t end up with noise crossing from one into the other because = of a coupling=20 effect. Once you have separate power domains, you need to make sure you = provide=20 enough of those power and ground pins or pads to each one and that = increases the=20 number of pads in your design which is also a problem, because if you = have more=20 pads it=E2=80=99s more area and less space along the edge of your = chip.=E2=80=9D

Noise must be decoupled at the substrate. =E2=80=9CMost processes = have very=20 well-defined guard ring rules and that typically comes from the foundry. = The=20 foundry itself has done a lot of that characterization. Theoretically, = if you=20 follow the design rules you=E2=80=99ve got a certain level of noise = isolation but it=20 depends on what you=E2=80=99re trying to isolate noise from. When you = get down into the=20 really small geometries the design rules get really tough,=E2=80=9D = Spruiell added.

According to a Synopsys white=20 paper, =E2=80=9Cadvanced processes are no longer driven by simple = spacing and=20 enclosure checks but now contain complex and situation dependent rules. = At 45-nm=20 there are almost 1,400 rules mostly described as complex mathematical = equations.=20 At 28- and 22-nm design rule counts exceed 1,800.=E2=80=9D

In this way, the foundries play a huge role in defining how the = designer can=20 implement isolation techniques.

At the end of the day, while the solutions to these problems sound = simple=20 (add more metal, more vias, more de-caps), Mentor=E2=80=99s Carrier = noted, =E2=80=9Cadding these=20 increases product cost. More layers, more drill time, more components = and space.=20 So good analysis in the hands of the engineer and designer can prevent = an over=20 conservative design and also ensure the product will work as planned, = reliably,=20 and over long periods of time.=E2=80=9D

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Tags: Apache Design Solutions, Cadence, I/O,=20 Mentor Graphics, noise, Synopsys

This entry was posted on = Thursday,=20 December 2nd, 2010 at 12:01 am and is filed under Top=20 Stories. You can follow any responses to this entry through = the RSS=20 2.0 feed. You can leave=20 a response, or trackback from your own site.

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