Analog-to-digital = converter -=20 Wikipedia, the free encyclopedia

Analog-to-digital=20 converter

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4-channel stereo multiplexed = analog-to-digital=20 converter WM8775SEDS made by Wolfson=20 Microelectronics placed on an X-Fi=20 Fatal1ty Pro sound=20 card.

An analog-to-digital converter (abbreviated ADC, = A/D or=20 A to D) is a device that converts a continuous=20 quantity to a discrete=20 time digital = representation. An ADC=20 may also provide an isolated measurement. The reverse operation is = performed by=20 a digital= -to-analog=20 converter (DAC).

Typically, an ADC is an electronic=20 device that converts an input analog voltage=20 or current=20 to a digital number proportional to the magnitude of the voltage or = current.=20 However, some non-electronic or only partially electronic devices, such = as rotary=20 encoders, can also be considered ADCs.

The digital output may use different coding schemes. Typically the = digital=20 output will be a two's=20 complement binary number that is proportional to the input, but = there are=20 other possibilities. An encoder, for example, might output a Gray code.

[edit]=20 Concepts

[edit]=20 Resolution

Fig. 1. An 8-level ADC = coding=20 scheme.

The resolution of the converter indicates the number of discrete = values it=20 can produce over the range of analog values. The values are usually = stored=20 electronically in binary=20 form, so the resolution is usually expressed in bits.=20 In consequence, the number of discrete values available, or "levels", is = a power=20 of two. For example, an ADC with a resolution of 8 bits can encode an = analog=20 input to one in 256 different levels, since = 2⁸ =3D 256. The=20 values can represent the ranges from 0 to 255 (i.e. unsigned integer) or = from=20 =E2=88=92128 to 127 (i.e. signed integer), depending on the = application.

Resolution can also be defined electrically, and expressed in volts. The minimum change = in=20 voltage required to guarantee a change in the output code level is = called the least=20 significant bit (LSB) voltage. The resolution Q of the ADC is = equal=20 to the LSB voltage. The voltage resolution of an ADC is equal to its = overall=20 voltage measurement range divided by the number of discrete voltage=20 intervals:

$3D"Q$

where N is the number of voltage intervals and = E_FSR=20 is the full scale voltage range. E_FSR is given by

$3D"E_$

where V_RefHi and V_RefLow are the = upper=20 and lower extremes, respectively, of the voltages that can be coded.

Normally, the number of voltage intervals is given by

$3D"N$

where M is the ADC's resolution in bits.

That is, one voltage interval is assigned per code level.

Example:

Coding scheme as in figure 1 (assume input signal x(t) =3D = Acos(t), A =3D=20 5V)
Full=20 scale measurement range =3D -5 to 5 volts
ADC resolution is 8 bits: 2⁸ =3D 256 quantization = levels=20 (codes)
ADC voltage resolution, Q =3D (10 V =E2=88=92 = 0 V) / 256 =3D=20 10 V / 256 =E2=89=88 0.039 V =E2=89=88 39 mV.

In practice, the useful resolution of a converter is limited by the = best signal-to-noi= se=20 ratio (SNR) that can be achieved for a digitized signal. An ADC can = resolve=20 a signal to only a certain number of bits of resolution, called the effective = number of=20 bits (ENOB). One effective bit of resolution changes the signal-to-noi= se=20 ratio of the digitized signal by 6 dB, if the resolution is limited = by the=20 ADC. If a preamplifier=20 has been used prior to A/D conversion, the noise introduced by the = amplifier can=20 be an important contributing factor towards the overall SNR.

[edit]=20 Response = type

Most ADCs are linear types. The term linear implies that the = range of=20 input values has a linear relationship with the output value.

Some early converters had a logarithmic response to directly = implement=20 A-law or =CE=BC-law coding.=20 These encodings are now achieved by using a higher-resolution linear ADC = (e.g.=20 12 or 16 bits) and mapping its output to the 8-bit coded values.

[edit]=20 Accuracy

An ADC has several sources of errors. Qu= antization=20 error and (assuming the ADC is intended to be linear) non-linearity are = intrinsic to any=20 analog-to-digital conversion. There is also a so-called aperture = error=20 which is due to a clock jitter=20 and is revealed when digitizing a time-variant signal (not a constant=20 value).

These errors are measured in a unit called the least = significant=20 bit (LSB). In the above example of an eight-bit ADC, an error of one = LSB is=20 1/256 of the full signal range, or about 0.4%.

[edit]=20 Quantization = error

Main article: Quantization=20 error

Quantization error (or quantization noise) is the difference between = the=20 original signal and the digitized signal. Hence, The magnitude of the=20 quantization error at the sampling instant is between zero and half of = one LSB.=20 Quantization error is due to the finite resolution of the digital = representation=20 of the signal, and is an unavoidable imperfection in all types of = ADCs.

[edit]=20 Non-linearity

All ADCs suffer from non-linearity errors caused by their physical=20 imperfections, causing their output to deviate from a linear function = (or some=20 other function, in the case of a deliberately non-linear ADC) of their = input.=20 These errors can sometimes be mitigated by calibration,=20 or prevented by testing.

Important parameters for linearity are integral=20 non-linearity (INL) and different= ial=20 non-linearity (DNL). These non-linearities reduce the dynamic range = of the=20 signals that can be digitized by the ADC, also reducing the effective = resolution=20 of the ADC.

[edit]=20 Aperture = error

This section's factual accuracy is disputed= .=20 Please help to ensure that disputed facts are reliably = sourced. See=20 the relevant discussion on the talk=20 page. (August = 2011)

Imagine digitizing a sine wave $3D"x(t)=3DA$ .=20 Provided that the actual sampling time uncertainty due to the = clock jitter is ,=20 the error caused by this phenomenon can be estimated as $3D"E_{ap}$ .

The error is zero for DC, small at low frequencies, but significant = when high=20 frequencies have high amplitudes. This effect can be ignored if it is = drowned=20 out by the quantizing error. Jitter requirements can be = calculated using=20 the following formula: $3D"\Delta$ ,=20 where q is the number of ADC bits.

Output size (bits)	Input frequency
1 Hz	44.1 kHz	192 kHz	1 MHz	10 MHz	100 MHz	1 GHz
8	1,243 =C2=B5s	28.2 ns	6.48 ns	1.24 ns	124 ps	12.4 ps	1.24 ps
10	311 =C2=B5s	7.05 ns	1.62 ns	311 ps	31.1 ps	3.11 ps	0.31 ps
12	77.7 =C2=B5s	1.76 ns	405 ps	77.7 ps	7.77 ps	0.78 ps	0.08 ps
14	19.4 =C2=B5s	441 ps	101 ps	19.4 ps	1.94 ps	0.19 ps	0.02 ps
16	4.86 =C2=B5s	110 ps	25.3 ps	4.86 ps	0.49 ps	0.05 ps	=E2=80=93
18	1.21 =C2=B5s	27.5 ps	6.32 ps	1.21 ps	0.12 ps	=E2=80=93	=E2=80=93
20	304 ns	6.88 ps	1.58 ps	0.16 ps	=E2=80=93	=E2=80=93	=E2=80=93
24	19.0 ns	0.43 ps	0.10 ps	=E2=80=93	=E2=80=93	=E2=80=93	=E2=80=93
32	74.1 ps	=E2=80=93	=E2=80=93	=E2=80=93	=E2=80=93	=E2=80=93	=E2=80=93

This table shows, for example, that it is not worth using a precise = 24-bit=20 ADC for sound recording if there is not an ultra low jitter = clock. One=20 should consider taking this phenomenon into account before choosing an = ADC.

Clock jitter is caused by phase=20 noise.^[1][2]=20 The resolution of ADCs with a digitization bandwidth between 1 MHz = and=20 1 GHz is limited by jitter.^[3]

When sampling audio signals at 44.1 kHz, the anti-aliasing = filter should have eliminated all frequencies above 22 kHz. The = input=20 frequency (in this case, 22 kHz), not the ADC clock frequency, is = the=20 determining factor with respect to jitter performance.^[4]

[edit]=20 Sampling = rate

The analog signal is continuous = in time = and it is=20 necessary to convert this to a flow of digital values. It is therefore = required=20 to define the rate at which new digital values are sampled from the = analog=20 signal. The rate of new values is called the sampling rate or = sampling=20 frequency of the converter.

A continuously varying bandlimited signal can be sampled (that is, = the signal=20 values at intervals of time T, the sampling time, are measured and = stored) and=20 then the original signal can be exactly reproduced from the = discrete-time=20 values by an interpolation=20 formula. The accuracy is limited by quantization error. However, this = faithful=20 reproduction is only possible if the sampling rate is higher than twice = the=20 highest frequency of the signal. This is essentially what is embodied in = the Sh= annon-Nyquist=20 sampling theorem.

Since a practical ADC cannot make an instantaneous conversion, the = input=20 value must necessarily be held constant during the time that the = converter=20 performs a conversion (called the conversion time). An input = circuit=20 called a sample=20 and hold performs this task=E2=80=94in most cases by using a capacitor to store = the analog=20 voltage at the input, and using an electronic switch or gate to = disconnect the=20 capacitor from the input. Many ADC integrated=20 circuits include the sample and hold subsystem internally.

[edit]=20 Aliasing

Main article: Aliasing

All ADCs work by sampling their input at discrete intervals of time. = Their=20 output is therefore an incomplete picture of the behaviour of the input. = There=20 is no way of knowing, by looking at the output, what the input was doing = between=20 one sampling instant and the next. If the input is known to be changing = slowly=20 compared to the sampling rate, then it can be assumed that the value of = the=20 signal between two sample instants was somewhere between the two sampled = values.=20 If, however, the input signal is changing rapidly compared to the sample = rate,=20 then this assumption is not valid.

If the digital values produced by the ADC are, at some later stage in = the=20 system, converted back to analog values by a digital= to=20 analog converter or DAC= ,=20 it is desirable that the output of the DAC be a faithful representation = of the=20 original signal. If the input signal is changing much faster than the = sample=20 rate, then this will not be the case, and spurious signals called = aliases=20 will be produced at the output of the DAC. The frequency of the aliased = signal=20 is the difference between the signal frequency and the sampling rate. = For=20 example, a 2 kHz sine wave being sampled at 1.5 kHz would be=20 reconstructed as a 500 Hz sine wave. This problem is called aliasing.

To avoid aliasing, the input to an ADC must be low-pass filtered to = remove=20 frequencies above half the sampling rate. This filter is called an anti-aliasing= filter,=20 and is essential for a practical ADC system that is applied to analog = signals=20 with higher frequency content.

Although aliasing in most systems is unwanted, it should also be = noted that=20 it can be exploited to provide simultaneous down-mixing of a = band-limited high=20 frequency signal (see undersampling=20 and frequency=20 mixer). The alias is effectively the lower heterodyne=20 of the signal frequency and sampling frequency.

[edit]=20 Dither

In A-to-D converters, performance can usually be improved using dither. This is a very = small=20 amount of random noise (white=20 noise), which is added to the input before conversion. Its effect is = to=20 cause the state of the LSB to randomly oscillate between 0 and 1 in the = presence=20 of very low levels of input, rather than sticking at a fixed value. = Rather than=20 the signal simply getting cut off altogether at this low level (which is = only=20 being quantized to a resolution of 1 bit), it extends the effective = range of=20 signals that the A-to-D converter can convert, at the expense of a = slight=20 increase in noise - effectively the quantization error is diffused = across a=20 series of noise values which is far less objectionable than a hard = cutoff. The=20 result is an accurate representation of the signal over time. A suitable = filter=20 at the output of the system can thus recover this small signal = variation.

An audio signal of very low level (with respect to the bit depth of = the ADC)=20 sampled without dither sounds extremely distorted and unpleasant. = Without dither=20 the low level may cause the least significant bit to "stick" at 0 or 1. = With=20 dithering, the true level of the audio may be calculated by averaging = the actual=20 quantized sample with a series of other samples [the dither] that are = recorded=20 over time.

A virtually identical process, also called dither or dithering,=20 is often used when quantizing photographic images to a fewer number of = bits per=20 pixel=E2=80=94the image becomes noisier but to the eye looks far more = realistic than the=20 quantized image, which otherwise becomes banded.=20 This analogous process may help to visualize the effect of dither on an = analogue=20 audio signal that is converted to digital.

Dithering is also used in integrating systems such as electricity = meters.=20 Since the values are added together, the dithering produces results that = are=20 more exact than the LSB of the analog-to-digital converter.

Note that dither can only increase the resolution of a sampler, it = cannot=20 improve the linearity, and thus accuracy does not necessarily = improve.

[edit]=20 Oversampling

Main article: Oversampling

Usually, signals are sampled at the minimum rate required, for = economy, with=20 the result that the quantization noise introduced is white noise spread = over the=20 whole pass band of the converter. If a signal is sampled at a rate much = higher=20 than the Nyquist=20 frequency and then digitally=20 filtered to limit it to the signal bandwidth there are the following = advantages:

digital filters can have better properties (sharper rolloff,=20 phase) than analogue filters, so a sharper anti-aliasing filter can be = realised and then the signal can be downsampled giving a better = result
a 20-bit ADC can be made to act as a 24-bit ADC with 256=C3=97=20 oversampling
the signal-to-noi= se=20 ratio due to quantization=20 noise will be higher than if the whole available band had been = used. With=20 this technique, it is possible to obtain an effective resolution = larger than=20 that provided by the converter alone
The improvement in SNR is 3 dB (equivalent to 0.5 bits) per = octave of=20 oversampling which is not sufficient for many applications. Therefore, = oversampling is usually coupled with noise shaping (see sigma-delta=20 modulators). With noise shaping, the improvement is 6L+3 dB per = octave=20 where L is the order of loop filter used for noise shaping. e.g. - a = 2nd order=20 loop filter will provide an improvement of = 15 dB/octave.

[edit]=20 Relative = speed and=20 precision

The speed of an ADC varies by type. The Wilkinson ADC is limited by = the clock=20 rate which is processable by current digital circuits. Currently, = frequencies up=20 to 300 MHz are possible. The conversion time is directly = proportional to=20 the number of channels. For a successive-approximation ADC, the = conversion time=20 scales with the logarithm of the number of channels. Thus for a large = number of=20 channels, it is possible that the successive-approximation ADC is faster = than=20 the Wilkinson. However, the time consuming steps in the Wilkinson are = digital,=20 while those in the successive-approximation are analog. Since analog is=20 inherently slower than digital, as the number of channels increases, the = time=20 required also increases. Thus there are competing processes at work. = Flash ADCs=20 are certainly the fastest type of the three. The conversion is basically = performed in a single parallel step. For an 8-bit unit, conversion takes = place=20 in a few tens of nanoseconds.

There is, as expected, somewhat of a tradeoff between speed and = precision.=20 Flash ADCs have drifts and uncertainties associated with the comparator = levels,=20 which lead to poor uniformity in channel width. Flash ADCs have a = resulting poor=20 linearity. For successive-approximation ADCs, poor linearity is also = apparent,=20 but less so than for flash ADCs. Here, non-linearity arises from = accumulating=20 errors from the subtraction processes. Wilkinson ADCs are the best of = the three.=20 These have the best differential non-linearity. The other types require = channel=20 smoothing in order to achieve the level of the Wilkinson.^[5][6]

[edit]=20 The = sliding scale=20 principle

The sliding scale or randomizing method can be employed to greatly = improve=20 the channel width uniformity and differential linearity of any type of = ADC, but=20 especially flash and successive approximation ADCs. Under normal = conditions, a=20 pulse of a particular amplitude is always converted to a certain channel = number.=20 The problem lies in that channels are not always of uniform width, and = the=20 differential linearity decreases proportionally with the divergence from = the=20 average width. The sliding scale principle uses an averaging effect to = overcome=20 this phenomenon. A random, but known analog voltage is added to the = input pulse.=20 It is then converted to digital form, and the equivalent digital version = is=20 subtracted, thus restoring it to its original value. The advantage is = that the=20 conversion has taken place at a random point. The statistical = distribution of=20 the final channel numbers is decided by a weighted average over a region = of the=20 range of the ADC. This in turn desensitizes it to the width of any given = channel.^[7][8]

[edit]=20 ADC types

These are the most common ways of implementing an electronic ADC:

A direct-conversion ADC or flash=20 ADC has a bank of comparators=20 sampling the input signal in parallel, each firing for their decoded = voltage=20 range. The comparator bank feeds a logic circuit = that=20 generates a code for each voltage range. Direct conversion is very = fast,=20 capable of gigahertz=20 sampling rates, but usually has only 8 bits of resolution or fewer, = since the=20 number of comparators needed, 2^N - 1, doubles with each = additional=20 bit, requiring a large, expensive circuit. ADCs of this type have a = large die=20 size, a high input capacitance,=20 high power dissipation, and are prone to produce glitches=20 at the output (by outputting an out-of-sequence code). Scaling to = newer=20 submicrometre technologies does not help as the device mismatch is the = dominant design limitation. They are often used for video,=20 wideband communications or other fast signals in optical = storage.
A suc= cessive-approximation=20 ADC uses a comparator to successively narrow a range that = contains the=20 input voltage. At each successive step, the converter compares the = input=20 voltage to the output of an internal digital= to=20 analog converter which might represent the midpoint of a selected = voltage=20 range. At each step in this process, the approximation is stored in a=20 successive approximation register (SAR). For example, consider an = input=20 voltage of 6.3 V and the initial range is 0 to 16 V. For the first = step, the=20 input 6.3 V is compared to 8 V (the midpoint of the = 0=E2=80=9316 V range). The=20 comparator reports that the input voltage is less than 8 V, so = the SAR is=20 updated to narrow the range to 0=E2=80=938 V. For the second = step, the input=20 voltage is compared to 4 V (midpoint of 0=E2=80=938). The comparator = reports the input=20 voltage is above 4 V, so the SAR is updated to reflect the input = voltage=20 is in the range 4=E2=80=938 V. For the third step, the input = voltage is compared=20 with 6 V (halfway between 4 V and 8 V); the comparator reports the = input=20 voltage is greater than 6 volts, and search range becomes = 6=E2=80=938 V. The=20 steps are continued until the desired resolution is reached.
A ramp-compare ADC produces a saw-tooth=20 signal that ramps up or down then quickly returns to zero. When = the ramp=20 starts, a timer starts counting. When the ramp voltage matches the = input, a=20 comparator fires, and the timer's value is recorded. Timed ramp = converters=20 require the least number of transistors.=20 The ramp time is sensitive to temperature because the circuit = generating the=20 ramp is often just some simple oscillator.=20 There are two solutions: use a clocked counter driving a DAC= and=20 then use the comparator to preserve the counter's value, or calibrate = the=20 timed ramp. A special advantage of the ramp-compare system is that = comparing a=20 second signal just requires another comparator, and another register = to store=20 the voltage value. A very simple (non-linear) ramp-converter can be=20 implemented with a microcontroller and one resistor and capacitor.^[9]=20 Vice versa, a filled capacitor can be taken from an integrator,=20 time-to-amplitude converter, phase=20 detector, sample=20 and hold circuit, or peak=20 and hold circuit and discharged. This has the advantage that a = slow comparator cannot = be=20 disturbed by fast input changes.
The Wilkinson ADC was designed by D. H. Wilkinson in 1950. = The=20 Wilkinson ADC is based on the comparison of an input voltage with that = produced by a charging capacitor. The capacitor is allowed to charge = until its=20 voltage is equal to the amplitude of the input pulse (a comparator = determines=20 when this condition has been reached). Then, the capacitor is allowed = to=20 discharge linearly, which produces a ramp voltage. At the point when = the=20 capacitor begins to discharge, a gate pulse is initiated. The gate = pulse=20 remains on until the capacitor is completely discharged. Thus the = duration of=20 the gate pulse is directly proportional to the amplitude of the input = pulse.=20 This gate pulse operates a linear gate which receives pulses from a=20 high-frequency oscillator clock. While the gate is open, a discrete = number of=20 clock pulses pass through the linear gate and are counted by the = address=20 register. The time the linear gate is open is proportional to the = amplitude of=20 the input pulse, thus the number of clock pulses recorded in the = address=20 register is proportional also. Alternatively, the charging of the = capacitor=20 could be monitored, rather than the discharge.^[10][11]
An integrating=20 ADC (also dual-slope or multi-slope ADC) applies = the=20 unknown input voltage to the input of an integrator=20 and allows the voltage to ramp for a fixed time period (the run-up = period).=20 Then a known reference voltage of opposite polarity is applied to the=20 integrator and is allowed to ramp until the integrator output returns = to zero=20 (the run-down period). The input voltage is computed as a function of = the=20 reference voltage, the constant run-up time period, and the measured = run-down=20 time period. The run-down time measurement is usually made in units of = the=20 converter's clock, so longer integration times allow for higher = resolutions.=20 Likewise, the speed of the converter can be improved by sacrificing=20 resolution. Converters of this type (or variations on the concept) are = used in=20 most digital voltmet= ers=20 for their linearity and flexibility.
A delta-encoded ADC or counter-ramp has an up-down = counter that feeds a = digital= =20 to analog converter (DAC). The input signal and the DAC both go to = a=20 comparator. The comparator controls the counter. The circuit uses = negative feedback=20 from the comparator to adjust the counter until the DAC's output is = close=20 enough to the input signal. The number is read from the counter. Delta = converters have very wide ranges and high resolution, but the = conversion time=20 is dependent on the input signal level, though it will always have a=20 guaranteed worst-case. Delta converters are often very good choices to = read=20 real-world signals. Most signals from physical systems do not change = abruptly.=20 Some converters combine the delta and successive approximation = approaches;=20 this works especially well when high frequencies are known to be small = in=20 magnitude.
A pipeline ADC (also called subranging quantizer) = uses two=20 or more steps of subranging. First, a coarse conversion is done. In a = second=20 step, the difference to the input signal is determined with a digital= =20 to analog converter (DAC). This difference is then converted = finer, and=20 the results are combined in a last step. This can be considered a = refinement=20 of the successive-approximation ADC wherein the feedback reference = signal=20 consists of the interim conversion of a whole range of bits (for = example, four=20 bits) rather than just the next-most-significant bit. By combining the = merits=20 of the successive approximation and flash ADCs this type is fast, has = a high=20 resolution, and only requires a small die size.
A sigma-delta ADC (also known as a delta-sigma ADC)=20 oversamples the desired signal by a large factor and filters the = desired=20 signal band. Generally, a smaller number of bits than required are = converted=20 using a Flash ADC after the filter. The resulting signal, along with = the error=20 generated by the discrete levels of the Flash, is fed back and = subtracted from=20 the input to the filter. This negative feedback has the effect of noise shaping = the error=20 due to the Flash so that it does not appear in the desired signal = frequencies.=20 A digital filter (decimation filter) follows the ADC which reduces the = sampling rate, filters off unwanted noise signal and increases the = resolution=20 of the output (sigma-delta = modulation, also called delta-sigma = modulation).
A time-interleaved ADC uses M parallel ADCs where each ADC = samples=20 data every M:th cycle of the effective sample clock. The result is = that the=20 sample rate is increased M times compared to what each individual ADC = can=20 manage. In practice, the individual differences between the M ADCs = degrade the=20 overall performance reducing the SFDR^[12].=20 However, technologies exist to correct for these time-interleaving = mismatch=20 errors.
An ADC with intermediate FM stage first uses a = voltage-to-frequency=20 converter to convert the desired signal into an oscillating signal = with a=20 frequency proportional to the voltage of the desired signal, and then = uses a=20 frequency=20 counter to convert that frequency into a digital count = proportional to the=20 desired signal voltage. Longer integration times allow for higher = resolutions.=20 Likewise, the speed of the converter can be improved by sacrificing=20 resolution. The two parts of the ADC may be widely separated, with the = frequency signal passed through an opto-isolator=20 or transmitted wirelessly. Some such ADCs use sine wave or square wave = frequency=20 modulation; others use pulse-fr= equency=20 modulation. Such ADCs were once the most popular way to show a = digital=20 display of the status of a remote analog sensor.^[13][14][15][16][17]

There can be other ADCs that use a combination of electronics and = other technologies:

A time-stretch=20 analog-to-digital converter (TS-ADC) digitizes a very wide = bandwidth=20 analog signal, that cannot be digitized by a conventional electronic = ADC, by=20 time-stretching the signal prior to digitization. It commonly uses a = photonic preprocessor frontend= =20 to time-stretch the signal, which effectively slows the signal down in = time=20 and compresses its bandwidth. As a result, an electronic backend = ADC, that would have been too slow to capture the original signal, can = now=20 capture this slowed down signal. For continuous capture of the signal, = the=20 frontend also divides the signal into multiple segments in addition to = time-stretching. Each segment is individually digitized by a separate=20 electronic ADC. Finally, a digital=20 signal processor rearranges the samples and removes any = distortions added=20 by the frontend to yield the binary data that is the digital = representation of=20 the original analog signal.

[edit]=20 Commercial analog-to-digital = converters

These are usually integrated=20 circuits.

Most converters sample with 6 to 24 bits=20 of resolution, and produce fewer than 1 megasample per second. Thermal=20 noise generated by passive components such as resistors masks the=20 measurement when higher resolution is desired. For audio applications = and in=20 room temperatures, such noise is usually a little less than 1 =CE=BCV (microvolt) of = white=20 noise. If the MSB corresponds to a standard 2 V of output signal, = this=20 translates to a noise-limited performance that is less than 20~21 bits, = and=20 obviates the need for any dithering.=20 As of February 2002, Mega- and giga-sample per second converters are = available.=20 Mega-sample converters are required in digital video=20 cameras, video=20 capture cards, and TV=20 tuner cards to convert full-speed analog video to digital video = files.=20 Commercial converters usually have =C2=B10.5 to =C2=B11.5 LSB = error in their=20 output.

In many cases, the most expensive part of an integrated circuit is = the pins,=20 because they make the package larger, and each pin has to be connected = to the=20 integrated circuit's silicon. To save pins, it is common for slow ADCs = to send=20 their data one bit at a time over a serial interface to = the=20 computer, with the next bit coming out when a clock signal changes = state, say=20 from 0 to 5 V. This saves quite a few pins on the ADC package, and = in many=20 cases, does not make the overall design any more complex (even microprocessors = which use=20 memory-mapped=20 I/O only need a few bits of a port to implement a serial bus=20 to an ADC).

Commercial ADCs often have several inputs that feed the same = converter,=20 usually through an analog multiplexer.=20 Different models of ADC may include sample=20 and hold circuits, instrumentation amplifiers=20 or differential=20 inputs, where the quantity measured is the difference between two = voltages.

[edit]=20 Applications

[edit]=20 Music = recording

ADCs are integral to current music reproduction technology. Since = much music=20 production is done on computers, when an analog recording is used, an = ADC is=20 needed to create the PCM=20 data stream that goes onto a compact=20 disc or digital music file.

The current crop of AD converters utilized in music can sample at = rates up to=20 192 kilohertz.=20 High bandwidth headroom allows the use of cheaper or faster anti-aliasing = filters of=20 less severe filtering slopes. The proponents of oversampling assert that = such=20 shallower anti-aliasing filters produce less deleterious effects on = sound=20 quality, exactly because of their gentler slopes. Others prefer entirely = filterless AD conversion, arguing that aliasing is less detrimental to = sound=20 perception than pre-conversion brickwall filtering. Considerable = literature=20 exists on these matters, but commercial considerations often play a = significant=20 role. Most^{[citation=20
needed]} high-profile recording studios record in=20 24-bit/192-176.4 kHz PCM or in DSD=20 formats, and then downsample or decimate the signal for Red-Book CD = production=20 (44.1 kHz) or to 48 kHz for commonly used for radio/TV = broadcast=20 applications.

[edit]=20 Digital = signal=20 processing

AD converters are used virtually everywhere where an analog signal = has to be=20 processed, stored, or transported in digital form. Fast video ADCs are = used, for=20 example, in TV=20 tuner cards. Slow on-chip 8, 10, 12, or 16 bit ADCs are common in microcontrollers. Very=20 fast ADCs are needed in Digita= l=20 storage oscilloscopes, and are crucial for new applications like software=20 defined radio.

[edit]=20 Electrical = Symbol

[edit]=20 Testing

Testing an Analog to Digital Converter requires an analog input = source,=20 hardware to send control signals and capture digital data output. Some = ADCs also=20 require an accurate source of reference signal.

The key parameters to test a SAR ADC are following:

DC Offset Error
DC Gain Error
Signal to Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Integral Non Linearity (INL)
Differential Non Linearity (DNL)
Spurious Free Dynamic Range
Power Dissipation

[edit]=20 See also

Audio=20 converter
Beta = encoder
Digital=20 signal processing
Qu= antization=20 (signal processing)
Modem
Differential= =20 linearity
Sample-an= d-hold=20 amplifier
Ideal = sampler
Integral=20 linearity

[edit]=20 Notes

^=20 Maxim App 800: "Design a Low-Jitter Clock for = High-Speed Data=20 Converters"
^=20 "Jitter effects on Analog to Digital and Digital to = Analog=20 Converters"
^=20 abstract: "The effects of aperture jitter and clock = jitter in=20 wideband ADCs" by Michael L=C3=B6hning and Gerhard Fettweis = 2007
^=20 "Understanding the effect of clock jitter on = high-speed=20 ADCs" by Derek Redmayne & Alison Steer 2008
^=20 Knoll=20 (1989, p. 664=E2=80=93665)
^=20 Nicholson=20 (1974, p. 313=E2=80=93315)
^=20 Knoll=20 (1989, p. 665=E2=80=93666)
^=20 Nicholson=20 (1974, p. 315=E2=80=93316)
^=20 Atmel Application Note AVR400: Low Cost A/D=20 Converter
^=20 Knoll=20 (1989, p. 663=E2=80=93664)
^=20 Nicholson=20 (1974, p. 309=E2=80=93310)
^=20 Vogel, = Christian=20 (February 2005). "The Impact of Combined Channel Mismatch Effects in=20 Time-interleaved ADCs". IEEE Transactions on Instrumentation and=20 Measurement 55 (1): 415-427. doi:<= A=20 class=3D"external text" = href=3D"http://dx.doi.org/10.1109%2FTIM.2004.834046" = rel=3D"nofollow">10.1109/TIM.2004.834046.
^=20 [www.analog.com/static/imported-files/tutorials/= MT-028.pdf=20 Analog Devices MT-028 Tutorial: "Voltage-to-Frequency Converters"] by = Walt=20 Kester and James Bryant 2009, apparently adapted from "Data conversion handbook" by Walter Allan Kester = 2005,=20 page 274
^=20 [ww1.microchip.com/downloads/en/AppNotes/00795a.= pdf=20 Microchip AN795 "Voltage to Frequency / Frequency to Voltage = Converter"] page=20 4: "13-bit A/D converter"
^=20 "Elements of electronic instrumentation and = measurement" by=20 Joseph J. Carr 1996, page 402
^=20 "Voltage-to-Frequency Analog-to-Digital=20 Converters"
^=20 "Troubleshooting Analog Circuits" by Robert A. = Pease 1991,=20 p. 130

[edit]=20 References

Allen, Phillip = E.;=20 Holberg, Douglas R., CMOS Analog Circuit Design, = ISBN 0= -19-511644-5
Kester, Walt, = ed. (2005), The Data Conversion Handbook, Elsevier: = Newnes, = ISBN 0= -7506-7841-0, http://www.analog.com/library/analogDialogue/archives/39= -06/data_conversion_handbook.html
Johns, David; = Martin, Ken,=20 Analog Integrated Circuit Design, = ISBN 0= -471-14448-7
Knoll, Glenn F. = (1989),=20 Radiation Detection and Measurement (2nd ed.), New York: John = Wiley=20 & Sons, pp. 665=E2=80=93666
Liu, Mingliang, = Demystifying=20 Switched-Capacitor Circuits, = ISBN 0= -7506-7907-7
Nicholson, P. = W. (1974),=20 Nuclear Electronics, New York: John Wiley & Sons,=20 pp. 315=E2=80=93316
Norsworthy,=20 Steven R.; Schreier, Richard; Temes, Gabor C. (1997), Delta-Sigma = Data=20 Converters, IEEE Press, = ISBN 0= -7803-1045-4
Razavi, Behzad = (1995),=20 Principles of Data Conversion System Design, New York, NY: IEEE = Press,=20 = ISBN 0= -7803-1093-4
Staller, Len = (February 24,=20 2005), "Understanding analog to digital converter = specifications",=20 Embedded Systems Design, http://www.embedded.com/showArticle.jhtml?articleID=3D60= 403334
Walden, R. H. = (1999), "Analog-to-digital converter survey and = analysis", IEEE=20 Journal on Selected Areas in Communications 17 (4): = 539=E2=80=93550, doi:<= A=20 class=3D"external text" href=3D"http://dx.doi.org/10.1109%2F49.761034" = rel=3D"nofollow">10.1109/49.761034,=20 ISSN 0733-8716, http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=3D7= 61034

[edit]=20 External = links

Wikibooks has a book on the topic of

Analo= g=20 and Digital Conversion

Counting=20 Type ADC A simple tutorial showing how to build your first = ADC.
An Introduction to Delta Sigma Converters A very = nice=20 overview of Delta-Sigma converter theory.
Digital Dynamic Analysis of A/D Conversion Systems = through=20 Evaluation Software based on FFT/DFT Analysis RF Expo East, = 1987
Which ADC Architecture Is Right for Your = Application?=20 article by Walt Kester
AN71=20 - The Care and Feeding of High Performance ADCs Real world circuit = and=20 layout advice
ADC and DAC Glossary Defines commonly used = technical=20 terms.
Introduction to ADC in AVR - Analog to digital = conversion=20 with Atmel microcontrollers
Signal processing and system aspects of = time-interleaved=20 ADCs.

Retrieved from "http://en.wikipedia.org/w/index.php?title=3D= Analog-to-digital_converter&oldid=3D479081613"

Categories: =

= Digital=20 signal processing
Electr= onic=20 circuits

Hidden categories:=20

Accuracy=20 disputes from August 2011
All = accuracy disputes
All=20 articles with unsourced statements
Articles=20 with unsourced statements from November = 2008

Analog-to-digital=20 converter

Contents

[edit]=20 Concepts

[edit]=20 Resolution

[edit]=20 Response = type

[edit]=20 Accuracy

[edit]=20 Quantization = error

[edit]=20 Non-linearity

[edit]=20 Aperture = error

[edit]=20 Sampling = rate

[edit]=20 Aliasing

[edit]=20 Dither

[edit]=20 Oversampling

[edit]=20 Relative = speed and=20 precision

[edit]=20 The = sliding scale=20 principle

[edit]=20 ADC types

[edit]=20 Commercial analog-to-digital = converters

[edit]=20 Applications

[edit]=20 Music = recording

[edit]=20 Digital = signal=20 processing

[edit]=20 Electrical = Symbol

[edit]=20 Testing

[edit]=20 See also

[edit]=20 Notes

[edit]=20 References

[edit]=20 External = links

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